1. Technical Field
The present invention relates in general to integrated circuits.
2. Description of the Related Art
In many conventional integrated circuits, circuit operation is timed utilizing a clock signal, which synchronizes the flow of data signals through the circuit. A key design consideration for such clocked circuits is the timing requirements of the data signal(s) with reference to the clock signal, including the setup and hold times for the data signal(s). The setup time refers to the required relative arrival times of the clock and data signals. Hold time refers to the time following a clock pulse during which the data signal must remain stable in order to guarantee that the data passed to the next circuit stage is correct. If circuit timing requirements are not met, for example, if a data signal fails to meet the required setup time, the circuit may output incorrect data, possibly cascading to cause a larger system error or failure.
Because integrated circuits embodying the same circuit design in practice experience a range of timing behaviors due to a number of conditions, like temperature, voltage reference variations, fabrication process variations, etc., the timing analysis phase of the circuit design process typically includes so-called “corner” analysis in order to qualify an integrated circuit design across a wide range of conditions. In performing corner analysis, the operative assumption is that if a design works under each extreme condition, then assuming monotonic behavior, the design is also qualified for all intermediate conditions.
To enable a circuit design to pass corner analysis, timing requirements are often relaxed by the addition of excess timing margin to the circuit timing, thus enabling the timing requirements to be met across a wide range of conditions. As will be appreciated, the introduction of excess timing margin in a circuit design, while ensuring correct circuit operations, will eventually cause to circuit to fail its performance requirements.